Speakers
Makoto Nagata
Kobe University
Talk title: Chip-Backside Vulnerability to Side Channel Attacks Exploiting Intentional Electromagnetic Interference
Abstract: Si substrate backside of an integrated circuit (IC) chip, more precisely, the backside surface of its Silicon substrate provides open areas for adversarial security attacks. An IC chip becomes vulnerable against electromagnetic (EM) interference in both emanation and irradiation particularly in flip-chip packaging. The talk covers EM side channel (SC) leakages over the Si substrate backside, additionally with intentional SC amplification according to design falsification. It also details the mechanisms of bit-flip errors in bistable circuits intentionally caused by high-voltage pulse (HVP) injection on the backside of the IC. The chip-backside vulnerability of an IC chip will be experimentally given with Si examples as well as analytically described with simulation models.
Makoto Nagata received the B.S. and M.S. degrees in physics from Gakushuin University, Tokyo, Japan, in 1991 and 1993, respectively, and the Ph.D. degree in electronics engineering from Hiroshima University, Hiroshima, Japan, in 2001. He is a full professor at Kobe University since 2009, and served for the dean of the graduate school of science, technology and innovation (2022-2023).
He chaired the technology directions subcommittee for ISSCC (2018-2022) and served for an executive committee member of the conference (2023-2025). He was the technical program chair (2010–2011), the symposium chair (2012–2013), and an executive committee member (2014–2015) for the symposium on VLSI circuits. He was an organizing committee chair of AsianHOST 2024. He was the IEEE Solid-State Circuits Society (SSCS) AdCom member (2020-2022) and appointed as the distinguished lecturer (2020-2021 and 2024-) and the chapters vice chair of the society (2022-). He is presently the president of Electronics Society of IEICE.
Edward Suh
NVIDIA
G. Edward Suh is a Senior Director of Research, and leads a group in security
and privacy research. He is also an Adjunct Professor in the School of Electrical and Computer
Engineering at Cornell University, where he served on the faculty from 2007 to 2023. Before joining
NVIDIA, he was a Research Scientist in the Fundamental AI Research (FAIR) team at Meta. He earned
a B.S. in Electrical Engineering from Seoul National University and an M.S. and a Ph.D. in Electrical
Engineering and Computer Science from the Massachusetts Institute of Technology (MIT). His research
interests include computer systems in general with particular focus on computer architecture and
security. His recent research focuses on building secure computing systems for secure and private
AI, and using AI to improve the security of computer systems. His past research received multiple
test-of-time awards and is widely recognized for the impact at the intersection of hardware and security.
For example, his work on Physical Unclonable Function (PUF) is now used in commercial products such as
Xilinx FPGAs for storing secret keys. His work on the AEGIS secure processor received a test-of-time
award for its contribution for trusted execution environments deployed across the industry today. He is a
Fellow of IEEE.
Todd Austin
University of Michigan
Todd Austin is the S. Jack Hu Collegiate Professor of Electrical Engineering and
Computer Science at the University of Michigan in Ann Arbor. His research interests include computer
architecture, robust and secure system design, hardware and software verification, and performance analysis
tools and techniques. From 2012-2017, Todd was the director of C-FAR, the Center for Future Architectures
Research, a multi-university SRC/DARPA funded center that was seeking technologies to scale the performance
and efficiency of future computing systems. Prior to joining academia, Todd was a Senior Computer Architect
in Intel’s Microcomputer Research Labs, a product-oriented research laboratory in Hillsboro, Oregon. Todd
is the first to take credit (but the last to accept blame) for creating the SimpleScalar Tool Set, a
popular collection of computer architecture performance analysis tools. Todd is co-author (with Andrew
Tanenbaum of Vrije Universiteit) of the undergraduate computer architecture textbook, “Structured Computer
Architecture, 6th Ed.” In addition to his work in academia, Todd is founder of SimpleScalar LLC, and co-founder
of Agita Labs Inc. and InTempo Design LLC. In 2002, Todd was a Sloan Research Fellow, and in 2007 he received
the ACM Maurice Wilkes Award for “innovative contributions in Computer Architecture including the SimpleScalar
Toolkit and the DIVA and Razor architectures.” Todd is an IEEE Fellow, and he received his PhD in Computer
Science from the University of Wisconsin in 1996.
Srini Devadas
Massachusetts Institute of Technology (MIT)
Srini Devadas is the Webster Professor of Electrical Engineering and Computer Science at the Massachusetts Institute of Technology (MIT). He received his MS and PhD from the University of California, Berkeley in 1986 and 1988, respectively. He joined MIT in 1988 and served as Associate Head of the Department of Electrical Engineering and Computer Science, with responsibility for Computer Science, from 2005 to 2011.
Devadas’s research interests span Computer-Aided Design (CAD), computer security and computer architecture and he has received significant awards from each discipline. He received the 1990 IEEE Transactions on CAD best paper award for work on synthesis for testability and the 1996 IEEE Transactions on VLSI Systems best paper award for work on power estimation. He received the 50th Design Automation Conference (DAC 2013) Top 10 Cited Author Award, for being among the top ten most cited DAC authors in DAC’s 50 year history and the DAC Best-Paper Hat-Trick Award, for winning DAC best paper awards three times. Devadas was elected a Fellow of the IEEE in 1999 for contributions to design automation.
Devadas and his students invented silicon Physical Unclonable Functions (PUFs) in 2002. PUFs are the technological basis of the founding of Verayo, a company focused on improving the security of computer hardware. Based on integrated-circuit manufacturing variation, Verayo has developed secure RFID chips that are in use in anti-counterfeiting applications and secret-key generation technology. Devadas’s papers on PUFs have received best paper awards at ACSAC 2002, HOST 2011 and HOST 2012.
In computer architecture, Devadas’s papers on analytical cache modeling and the Aegis single-chip secure processor were recognized as influential papers in the “25 Years of the International Conference on Supercomputing” volume. His work on hardware-information flow tracking published in the 2004 ASPLOS received the ASPLOS Most Influential Paper Award in 2014.
Christof Paar
Max Planck Institute
Christof Paar is Director at the Max Planck Institute for Security and Privacy, Germany, and affiliated with the University of Massachusetts Amherst. His research interests include hardware security, physical-layer security, applied cryptography and security analysis of real-world systems. He has co-founded Cryptographic Hardware and Embedded Systems (CHES), the leading international conference on applied cryptography. Christof is one of the designers of the popular lightweight cipher PRESENT and co-author of the widely used textbook Understanding Cryptography. He is a fellow of IEEE and IACR (International Association for Cryptologic Research), and has given invited talks at Cambridge, Harvard, MIT, Oxford, Stanford and Yale. He co-founded ESCRYPT Inc., a leading provider for automotive security solutions, which is now part of Bosch.
Shivam Bhasin
Nanyang Technical University (NTU)
Shivam Bhasin received the bachelor’s degree from UP Tech, India, in 2007, the master’s degree from Mines Saint-Etienne, France, in 2008, and the PhD degree from Telecom Paristech, in 2011. He is a senior research scientist and principal investigator at Physical Analysis and Cryptographic Engineering Laboratory, Temasek labs, Nanyang Technical University Singapore, since 2015. His research interests include embedded security, trusted computing and secure designs. Before NTU, Shivam held position of Research Engineer in Institut Mines-Telecom, France. He was also a visiting researcher at UCL, Belgium (2011) and Kobe University, Japan (2013). He regularly publishes at top peer reviewed journals and conferences. Some of his research now also forms a part of ISO/IEC 17825 Standard. He is a member of the IEEE.
Dominic Rizzo
zeroRISC
Dominic Rizzo is the founder and CEO of zeroRISC. His research interests include hardening silicon implementations against physical attacks and side channels, trustworthy authenticators, and formal methods to provide implementation security and correctness guarantees. He received a B.S. in aerospace engineering from the Massachusetts Institute of Technology and an M.S. in computer science from the California Institute of Technology.
Sharad Malik
Princeton University
Sharad Malik (F’02) received the B.Tech. degree in electrical engineering from the Indian Institute of Technology Delhi, New Delhi, India, in 1985, and the M.S. and Ph.D. degrees in computer science from the University of California at Berkeley, Berkeley, CA, USA, in 1987 and 1990, respectively.
He served as the Director of the Keller Center for Innovation in Engineering Education, Princeton University, Princeton, NJ, USA, from 2006 to 2011. He is the George Van Ness Lothrop Professor of Engineering with Princeton University and the Chair of the Department of Electrical Engineering. He has served as the Director of the multi-university MARCO Gigascale Systems Research Center, Berkeley, CA, USA, from 2009 to 2012, and as the Associate Director of the Center for Future Architectures Research, Ann Arbor, MI, USA, from 2013 to 2016. His research in functional timing analysis and propositional satisfiability has been widely used in industrial electronic design automation tools. His current research interest includes design methodology and design automation for computing systems.
Dr. Malik has received the IEEE/ACM Design Automation Conference Award for the most cited paper in the 50-year history of the conference in 2013, the Computer-Aided Verification Award for fundamental contributions to the development of high-performance Boolean satisfiability solvers in 2009, the IEEE/ACM International Conference on Computer-Aided Design Ten Year Retrospective Most Influential Paper Award in 2011, the IEEE CEDA A. Richard Newton Technical Impact Award in Electronic Design Automation in 2017, the Princeton University Presidents Award for Distinguished Teaching in 2009, the IIT Delhi Distinguished Alumni Award in 2009, as well as several other research and teaching awards. He is a fellow of the ACM.